1. Field of the Invention
The present invention relates to an image sensor, and more particularly, to an image sensor and a method for manufacturing the same, in which a maximization of a light receiving area of a photo diode and a minimization in a scale of formation of an element isolating region result from an improvement of a layout of the photo diode.
2. Description of the Related Art
Recently, with a rapid development of the electric/electronic technologies, various electronics, such as video cameras, digital still cameras, minicams adapted personal computers (PC), minicams adapted for mobile phones, and so forth, employing image sensor technologies have been widely developed and used.
Traditionally, as a conventional image sensor as described above, charge coupled devices (CCDs) have been generally used. However, such CCDs have drawbacks in high driving voltages, requiring separate additional support circuits, and having high per-unit prices, so that the usage thereof has been declining.
Recently, as an image sensor for overcoming the disadvantages of the CCD, attention is being focused on Complementary Metal Oxide Semiconductor (CMOS) image sensors. Since the CMOS image sensors are manufactured based on a series of CMOS circuit technologies, contrary to the existing CCD, they have advantages which include low driving voltages, obviating additional support circuits, low per-unit prices, etc.
Under such conventional technology systems, as shown in FIG. 1, unit cells C1, C2, C3 and C4 of the CMOS image sensor may be arranged together on a semiconductor substrate, forming a series of cell groups C.
Herein, respective unit cells C1, C2, C3 and C4 may have a construction including a combination of, for example, a photo diode (PD), a reset transistor (Rx), a drive transistor (Dx) and a select transistor (Sx). A region of the photo diode, an active region around a reset gate electrode 2, an active region around a drive gate electrode 3, an active region around a select gate electrode 4 and so forth are lightly or heavily doped with impurity ions, and around the respective unit cell C1, C2, C3 and C4, an element isolating layer 6 is formed to electrically separate the corresponding unit cells from each other.
Herein, the photo diode serves to generate and store a certain level of an electron-hole pair through receiving light incident from exterior. The reset transistor (Rx) may serve to reset the electron-hole pair generated and stored by the photo diode PD to its initial state. The drive transistor Dx may serve as a source follower buffer amplifier. Finally, the select transistor Sx may serve as a switching device and an addressing device.
In the conventional CMOS image sensor having such construction, as described above, the element isolating layer 6 may be formed around the respective unit cells C1, C2, C3 and C4 so as to electrically separate the corresponding unit cells C1, C2, C3 and C4. In this case, the occupying area of the photo diode PD is typically greatly reduced in proportion to the occupying area of the element isolating layer 6, so that the fill factor of the photo diode may be greatly reduced.
In case that the occupying area of the photo diode PD is greatly reduced by occupying area of the element isolating layer 6, resulting in a reduction of the fill factor of the photo diode, the quantity of light the photo diode PD can receive from the exterior may also be greatly reduced, thus greatly reducing the quality of the finished CMOS image sensor.
Meanwhile, under the conventional systems, for forming the element isolating layer 6, an etching process for a semiconductor substrate is typically performed, so that the semiconductor substrate is typically damaged by mechanical/chemical shocks applied during the etching process. In this case, when the photo diode PD is formed on an active region of the semiconductor substrate defined by the isolating layer 6 without any separate mitigating steps, a series of phenomena of current leakage due to the above damages is typically generated at interfaces L1, L2, L3 and L4 between the element isolating layer 6 and the photo diode.
When the current leakage between the element isolating layer 6 and the photo diode PD continues due to the damage of the semiconductor substrate caused by etching the element isolating layer 6, the electron-hole pair generated by the photo diode PD can not be conducted normally, which greatly reduces the quality of the finished CMOS image sensor.
Of course, if the occupying area of the photo diode PD is greatly reduced, the problems of reduction in the fill factor of the photo diode PD due to an intrusion of the element isolating layer 6, and the generation of current leakage at the interfaces L1, L2, L3 and L4 between the element isolating layer 6 and the photo diode PD, can be greatly reduced. However, in this case, electrical impacts between unit cells are typically inevitable, so that, in conventional sensors, a solution to address the problems caused by the serious defects generated by the element isolating layer 6 is desired.